1. Field of the Invention
This invention relates to memory circuits and more particularly to erase and programming operations of flash memory and EPROM circuits.
2. Description of the Relevant Art
It is well known in flash memory technology that the size of a memory cell can be reduced if hot electron injection is employed for programming operations and if Fowler-Nordheim tunneling is employed for erase operations. To employ hot electron injection for programming, an external high voltage supply "Vpp", which is typically 12 volts, is required. Programming from the read supply voltage "Vcc", which is typically five volts, is ordinarily not possible since the read supply voltage level is insufficient to induce hot electron injection. Therefore, in these memory devices, two separate external power supplies, Vpp and Vcc, must be provided to the circuit.
During programming of the flash memory device, the gate junction of a memory cell transistor is driven by a voltage of approximately 12 volts. Due to the high impedance at the gate terminal, only a small current is required to charge the gate in the required time, typically less than 100 .mu.A. On the other hand, the drain junction of the memory cell transistor is driven by a voltage of approximately six volts. A relatively high current of typically 1 mA per cell must be provided to the drain junction. Therefore, approximately 8 mA is required for a standard byte architecture during programming.
During erase operations, Fowler-Nordheim tunneling can be employed. Typically for a flash memory device, a large number of cells are erased simultaneously. This involves putting a high voltage of approximately 12 volts on the source junctions of the memory cells. Each cell may be leaking at this voltage approximately 10 nA, depending upon the exact process and temperature (source junction breakdown voltage). Thus, approximately 2.5 mA of current flows for a 256K byte chip and approximately 10 mA of current flows for a 1 megabyte device.
Approaches for eliminating the requirement of two separate power supplies (Vpp and Vcc) in such flash memory devices have been proposed. One approach has been to scale the memory transistor dimensions, and particularly L effective, to reduce the drain voltage necessary for programming. This approach, which must demonstrate sufficient programming efficiency at the lower limit of the Vcc specified range, has been unreliable so far.